1. Field of the Invention
The present invention generally relates to an integrated circuit, in particular, to a power metal-oxide-semiconductor (MOS) transistor die with temperature sensing function and an integrated circuit.
2. Description of Related Art
FIG. 1 is a drawing schematically illustrating a circuit of a conventional temperature sensor. Referring to FIG. 1, a temperature sensor uses a bipolar junction transistor (BJT) 12, such as NPN or PNP, and a current source 14. The PN junction would generate different voltage in accordance with different temperature. A comparator 16 compares the generated voltage with a voltage, which is not related to temperature. For example, the voltage bias at the PN junction is 0.4V when at 160° C., then the voltage 0.4 V is set as the preset value. Then, a temperature protection signal OTP is outputted when the voltage is greater than 0.4V for a purpose of protecting the integrated circuit (IC) from overheating which can stop the operation which may cause high temperature.
FIG. 2 is drawing schematically illustrating a top view of conventional IC deployment. The IC is constituted of dies in various functions and each die is formed from multiple cells. Referring to FIG. 2, an IC 200 includes power MOS transistor dies 20, 22 and controller die 24. In general, the temperature sensor is configured in the controller die 24. However, when the IC 200 includes the power MOS transistor dies 20, 22 and the controller die 24, the power MOS transistor dies 20, 22 would be a region with highest temperature of the whole IC because a large current would flow through the power MOS transistor dies 20, 22. However, the temperature sensed by the conventional sensing technology is not at the highest temperature. Thus, if the temperature sensor is configured in the controller die 24, it cannot have high temperature protection at all for the IC 200 and the IC 200 may be easily burnt down due to over heating.
FIG. 3A is a drawing, schematically illustrating an equivalent circuit for the conventional power MOS transistor die. FIG. 3B is a drawing, schematically illustrating the cross-sectional view of structure of the power MOS transistor die in FIG. 3A. The power MOS transistor die 30 shown in FIG. 3B has three NMOS cells with same structure. The indications of “PHASE”, “LG”, and “GND” respectively represent a phase terminal, a control terminal, and a ground terminal. The indications of “G”, “D”, and “S” respectively represent a gate, a drain and a source. The indications of “n+”, “n-”, “p+”, “pw”, and “SiO2” respectively represent a highly doped n-type region, a lowly doped n-type region, a highly doped p-type region, p well region, and silicon oxide region. The detail structure of power MOS transistor die is known to the one with ordinary skill in the art, and the detail structure is omitted in the following descriptions.